Generally, the goals of integrated circuit design are to optimize integrated circuit density, timing and various other parameters (e.g., electrical parameters) in order to develop products that meet desired performance specifications at a relatively low-cost and within a relatively fast turn-around time. There are various design options that can be used to meet these goals. For example, an application-specific integrated circuit (ASIC) refers to an integrated circuit that is at least partially custom-designed to perform a particular function. Various different types of ASIC design techniques are well known in the art and include, but are not limited to, standard cell ASIC design, mask-programmable gate array ASIC design, field-programmable gate array ASIC design, structured ASIC design, full custom ASIC design, or combinations thereof (e.g., embedded array ASIC design, which combines standard cell and gate array ASIC design).
In any case, integrated circuit design typically begins with a high-level description of the integrated circuit. This high-level description sets out the requirements for the integrated circuit chip and is stored on a data storage device in, for example, a hardware description language (HDL), such as VHDL or Verilog. Next, a logic synthesis tool can synthesize the high-level description into low-level constructs. For example, in the case of ASIC design the high-level description can be synthesized using library elements (e.g., standard cells in standard cell ASIC design or gate array base cells in gate array ASIC design). That is, the logic synthesis tool can synthesize a gate-level netlist from the high-level description. After logic synthesis, a placement tool can establish placement (i.e., location on the integrated circuit chip) of the library elements. Then, a routing tool can perform routing (e.g., can define the wires that will interconnect the library elements) and a timing analysis tool can perform timing analysis. Logic synthesis, placement, routing, and timing can be iteratively repeated, as necessary, to complete the design.
Following completion of the design, a design rule checking tool can determine if all design rules for a given technology have been met. Such design rules can include, for example, minimum and maximum density requirements for specific features at different mask levels (e.g., diffusion regions within the semiconductor substrate, deep trenches for deep trench isolation and/or deep trench capacitors within the substrate, polysilicon features on the semiconductor substrate, local interconnect features for connecting diffusion, polysilicon and/or deep trench features, metal features in the metal levels, via interconnect features for connecting metal levels etc.). These density requirements are typically set to minimize variation in the completed mask image on the product after lithographic, planarization, or etch processing. If a minimum density requirement is not met by the completed design, additional shapes can be added in open spaces within the design. For example, if the minimum density requirement for some specific features (e.g., deep trenches, polysilicon features, local interconnect features, metal features, via features, etc.) is not met, fill shapes (also referred to in the art as non-functional shapes, electrically inactive shapes, dummy shapes, etc.) corresponding to that feature can be placed at the appropriate mask level within open spaces in the integrated circuit chip regions on the semiconductor wafer and/or within open spaces between the integrated circuit chip regions (i.e., within kerf regions) in order to meet that minimum density requirement.
Following the addition of any fill shapes, a mask layout generation tool can generate a mask layout based on data and information accumulated during the previous processing. This mask layout can define, in hierarchical form, the detailed geometric shapes, text labels, and other information required for each mask level to be used in the actual fabrication of the integrated circuit under design. This mask layout can be stored, for example, in an industry standard database file format, such as Graphic Data System II (GDSII) or Oasis. The mask layout can subsequently proceed to tape-out (e.g., can be released to manufacturing, can be released to a mask house, can be sent to another design house, can be sent back to a customer, etc.).
Unfortunately, as a result of adding shapes to the open spaces in a completed design in order to meet design rules, the surface areas of the integrated circuit chip regions and/or the kerf regions in between are often increased to accommodate the added fill shapes, thereby reducing the number of integrated circuit chips per semiconductor wafer and increasing manufacturing costs.